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asix electronics corporation first released date : apr/09/1999 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw AX88872P 10/100base dual speed ? swipeater ? controller 10/100base dual speed 8-port repeater with 4-port switch document no.: ax872-13 / v1.3 / aug. 11 ? 99 features s upport 8 10/100mbps rmii i/f repeater ports and 2 10/100mbps rmii/mii switch ports ieee 802.3u repeater compatible support virtual switch mode and master/slave m ode for the cascade application build in 4-ports 10/100mbps switch engine with following features low cost ssram interface to reduce system cost one or two 64k*32bit ssram to buffer packets 4/8 k mac address entry table is supported auto learning and filtering aging the mac address table is supported optionally three forwarding modes are supported : store- a n d -forward, fragment-free and auto -forward flow-control is supported optionally. 802.3x flow control is supported in full duplex mode back-pressure base flow control is supported in half duplex mode ext. buffer memory auto testing routing and learning at wire speed (148800 packets/sec at 100mbps) up-to 4 repeaters can be cascaded for vertical expansion up-to 3 chips can be cascaded locally for horizontal expansion all ports can be separately isolated or partitioned in response to fault condition separate jabber and partition state machines for each port per-port led display for jabber, partition, activity. ram test fail and collision, buffer utilization (%) and global traffic utilization (%) for 10/100mbps presentation power on led diagnosis. all the led display will follow the ? on-off-on-off-normal ? operation procedure during/after power on reset 50mhz operation, 3.3volt and 208-pin pqfp product description the ax88872 10/100mbps dual speed ? swipeater ? controller is ? a dual speed repeater with build in 4-port s switch function ? it is design for low cost dumb hub application. the ax88872 directly supports up-to eight 10/100mbps automatic links rmii interfaces. maximum up-to 96 repeater ports can be constructed by stacking 1 ax88872 and 2 ax88873 chips horizontally and then cascading 4 horizontal board s vertically. about the build in 4-port switch : t he switch port 3 is fixed to 10mbps speed and connect s to 10mbps repeater segment, the switch port 2 is fixed to 100mbps and connect s to 100m repeater segment. the switch ports 0 and 1 are connected to external mii or rmii interfaces for various applications. for example, one port is use d for down link and the other is used for up link to exten d the network topology. the other case is one port for up link and the other port f or server. the ax88872 is designed base on ieee 802.3u clause 27 ? repeater for 100mb/s base-band networks ? it is fully compatible with ieee 802.3u standard. please refer ax873- 12 .doc to get more information about ax88873. system block diagram always contact asix for possible updates before starting a design. this data sheet contain s new products information. asix electronics reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. ax88873 #1 repeater controller buffer 100mbps horizontal cascade 10mbps and 100mbps vertical cascade up to 4 stacks ax88873 #0 repeater controller ax88872 #0 swipeater controller 10mbps horizontal cascade 2 quad rmii phy 2 quad rmii phy 2 quad rmii phy phy for up-link phy for down-link or server
asix electronics corporation 2 confidential AX88872P swipeater controller preliminary contents 1.0 ax88872 overview ................................ ................................ ................................ ................................ ....... 4 1.1 g eneral d escription ................................ ................................ ................................ ................................ ...... 4 1.2 ax88872 b lock d iagram : ................................ ................................ ................................ .............................. 5 1.3 p in c onnection d iagram ................................ ................................ ................................ ............................... 6 2.0 pin description ................................ ................................ ................................ ................................ ........... 7 2.1 rmii interface for repeater ports ................................ ................................ ................................ ............... 7 2.1.1 repeater port 0 ................................ ................................ ................................ ................................ .......... 7 2.1.2 repeater port 1 ................................ ................................ ................................ ................................ .......... 7 2.1.3 repeater port 2 ................................ ................................ ................................ ................................ .......... 8 2.1.4 repeater port 3 ................................ ................................ ................................ ................................ .......... 8 2.1.5 repeater port 4 ................................ ................................ ................................ ................................ .......... 8 2.1.6 repeater port 5 ................................ ................................ ................................ ................................ .......... 8 2.1.7 repeater port 6 ................................ ................................ ................................ ................................ .......... 9 2.1.8 repeater port 7 ................................ ................................ ................................ ................................ .......... 9 2.2 mii/rmii interface for switch ports ................................ ................................ ................................ ........... 9 2.2.1 switch port 0 ................................ ................................ ................................ ................................ .............. 9 2.2.2 switch port 1 ................................ ................................ ................................ ................................ ............ 10 2.3 e xpansion b us i nterface for 100 m bps ................................ ................................ ................................ ....... 11 2.4 e xpansion b us i nterface for 10 m bps ................................ ................................ ................................ ......... 11 2.5 led d isplay ................................ ................................ ................................ ................................ .................. 12 2.6 b uffer memory pins group ................................ ................................ ................................ ........................... 13 2.7 m iscellaneous ................................ ................................ ................................ ................................ .............. 14 2.8 p ower on configuration setup signals cross reference table ................................ ................................ 15 3.0 functional description ................................ ................................ ................................ ...................... 18 3.1 r epeater s tate m achine ................................ ................................ ................................ .............................. 18 3.2 rxe /txe c ontrol ................................ ................................ ................................ ................................ ...... 18 3.3 j abber s tate m achine ................................ ................................ ................................ ................................ .. 18 3.4 p artition s tate m achine ................................ ................................ ................................ ............................. 18 3.5 o peration of the b uilt -i n s witch ................................ ................................ ................................ ............... 19 3.5.1 packet filtering and forwarding process ................................ ................................ ................................ 19 3.5.2 mac address learning and aging process ................................ ................................ .............................. 19 3.5.3 flow control process ................................ ................................ ................................ ............................... 19 3.6 led d isplay i nterface ................................ ................................ ................................ ................................ 20 4.0 internal registers ................................ ................................ ................................ ................................ 22 5.0 electrical specification and timing ................................ ................................ .......................... 23 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ........................ 23 5.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 23 5.3 dc c haracteristics ................................ ................................ ................................ ................................ ..... 23 5.4 ac specifications ................................ ................................ ................................ ................................ ......... 24 5.4.1 lclk ................................ ................................ ................................ ................................ ....................... 24 5.4.2 reset timing ................................ ................................ ................................ ................................ ............ 24 5.4.3 rmii interface timing tx & rx ................................ ................................ ................................ ............... 25 5.4.4 mii interface timing tx & rx ................................ ................................ ................................ ................. 26 5.4.5 sram read cycle ................................ ................................ ................................ ................................ ...... 27 5.4.6 sram write cycle ................................ ................................ ................................ ................................ ..... 28 5.4.7 led display ................................ ................................ ................................ ................................ ......... 29 5.4.8 led display after reset ................................ ................................ ................................ ........................... 29
asix electronics corporation 3 confidential AX88872P swipeater controller preliminary 5.4.9 repeater id daisy chain ................................ ................................ ................................ ......................... 30 6.0 package information ................................ ................................ ................................ ........................... 31 appendix a: system applications ................................ ................................ ................................ .......... 32 a.1 16- port (24- port ) repeater with 2- port switch ................................ ................................ ......................... 32 a.2 16- port repeater with up to 4 stacks ................................ ................................ ................................ ......... 32 a.3 8- port standalone repeater with 2- port switch ................................ ................................ ...................... 33 a.4 16- port repeater with up to 4 stacks of ax88871a compatible mode ................................ .................... 33 a.5 16- port repeater with up to 4 stacks and more switch ports ................................ ................................ .. 34 appendix b: design note ................................ ................................ ................................ ............................. 35 b.1 u sing s tation m anagement (sta) c onnection ................................ ................................ ........................ 35 b.2 u sing mii i/f connects to mac ................................ ................................ ................................ .................. 36 figures f ig - 1 ax88872 b lock d iagram ................................ ................................ ................................ ............................. 5 f ig - 2 p in c onnection d iagram ................................ ................................ ................................ .............................. 6 f ig - 3 a pplication for led display ................................ ................................ ................................ ..................... 21
asix electronics corporation 4 confidential AX88872P swipeater controller preliminary 1.0 ax88872 overview 1.1 general description the ax88872 that built in a switch is not only a simple repeater but also it provide 2 repeater expan s ion bus es for 10m and 100m respectively. so the cascade function of the ax88872 can be backward compat i ble with the ax88871a ? bripeater ? in virtu al switch mode . also the ax88872 can support master/slave m ode in stack application . that all the repeater stack system form s one 100mbps segment and one 10mbps segment in master/slave m ode. the two segments are communication via the switch of the master chip . in general, u sing rmii interface for 8 repeater ports can simplify the design and also provide a low cost solution with rmii quad/octet phy and low cost 64kx32 ssram as buffer memory . in additional, the ax88872 provides two 10 / 100m mii/rmii switch ports alternative for up-link and down-link function . ax88872 has counterpart ax88873 that is a simple dual - speed repeater controller without built-in switch. t he switch port 3 is fixed to 10mbps speed and connect to 10mbps repeater segment, the switch port 2 is fixed to 100mbps and connect to 100m repeater segment. the other switch ports 0 and 1 are connected to external mii or rmii interfaces for various applications. the built-in switch provides 4/8 k look-up table that can learn, route and age with mac address of each packet automatically for packet forwarding and filtering. that is, the ax88872 forwards and filters packets with da (destination address) and the table. the performances of routing and learning fit wire speed (148800 packets/sec at 100mbps). the switch provides three packet forwarding mode: store-and- forward , fragment-free (i.e., safe cut- through) and auto mode. dynamically the switch selects optimum mode for packet forwarding based on network quality. during transmission, the data is obtained from the buffer memory and routed to the destination port. for half-duplex operation, when collision occurs, the mac control ler will back off and retransmit in accordance to the ieee802.3 specification. the switch also support flow-control mechanism. for full duplex operation mode, 802.3x flow control is supported. for half-duplex operation, an optional jamming based flow control is available to avoid loss of data. this is also well known as back - pressure. the flow control function is optional.
asix electronics corporation 5 confidential AX88872P swipeater controller preliminary 1. 2 ax88872 block diagram: 10/100 q-phy 10/100 q-phy rmii i/f rmii /mii translation for repeater port 0 -7 repeater state machine of 100mbps led interface cascade arbitration logic of 100mbps repeater state machine of 10mbps cascade arbitration logic of 10mbps per port jabber detection per port partition detection built in 4 port switch p0 p1 p2 p3 rmii /mii translation for switch port 0 and 1 ext ssram interface for up link for down link or server fig - 1 ax88872 block diagram
asix electronics corporation 6 confidential AX88872P swipeater controller preliminary 1. 3 pin connection diagram fig - 2 pin connection diagram 1 5 6 4 7 2 3 8 9 10 11 12 13 14 15 16 17 18 19 23 24 22 20 21 48 49 50 51 52 25 29 30 28 31 26 27 32 33 34 35 36 37 38 39 40 41 42 43 47 46 44 45 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 145 146 147 150 148 149 153 151 152 154 156 155 133 134 135 138 136 137 141 139 140 142 144 143 121 122 132 109 110 111 114 112 113 117 115 116 118 120 119 124 123 125 126 127 128 129 131 130 208 207 206 205 204 203 202 201 200 199 197 198 196 195 194 193 192 191 190 188 189 187 186 185 184 183 182 181 179 180 178 177 176 175 174 173 172 170 171 169 168 167 166 165 164 163 161 162 160 159 158 157 53 vss vdd vss vss hird_odir hird[1] hird[3] hird_ck hird[2] /hird_v led_ck vss hird[0] vdd vdd vss vss vss led<1> led<0> vss vss /hir_acto[3] /hir_acto[2] /hir_acto[1] /hir_acto[0] vdd vdd txen0 txd0[0] txd0[1] rxd0[0] rxd0[1] crs_dv0 txen1 crs_dv1 txd1[0] txd1[1] rxd1[0] rxd1[1] crs_dv2 rxd2[0] txen2 txd2[0] rxd2[1] txd2[1] rxd3[0] crs_dv3 rxd3[1] txen3 txd3[0] txd3[1] crs_dv4 rxd4[0] txd4[1] txd4[0] txen4 rxd4[1] txd5[1] rxd5[1] txd5[0] txen5 crs_dv5 rxd5[0] crs_dv6 rxd6[1] rxd6[0] txd6[0] txd6[1] txen6 crs_dv7 rxd7[1] rxd7[0] txd7[0] txen7 txd7[1] tird[1] tird[3] tird_ck tird[2] /tird_v tird[0] tird_odir /tir_acto[3] /tir_acto[2] /tir_acto[1] /tir_acto[0] /tir_acti[3] /tir_acti[2] /tir_acti[1] /tir_acti[0] /hir_acti[3] /hir_acti[2] /hir_acti[1] /hir_acti[0] ax88872 vss mdio mdc /lhir_act[2] /lhir_act[1] /lhir_act[0] /ltir_act[2] /ltir_act[1] /ltir_act[0] srxclk1 srxd1[2] scrs1 srxdv1 srxd1[0] srxd1[1] srxd1[3] stxd1[0] stxd1[1] stxd1[3] stxen1 stxd1[2] stxclk1 scol_sp1 stxd0[1] stxen0 stxclk0 srxd0[0] srxd0[1] srxd0[2] stxd0[0] stxd0[3] srxclk0 stxd0[2] scol_sp0 srxdv0 scrs0 srxd0[3] bma12 bma5 bma1 vss bma4 bma0 bma6 bma11 bma14 bma15 bma3 bma10 bma2 bma16 bma7 bma13 bmd24 bmd28 bmd27 bmd31 bmd26 bmd25 bmd29 bmd30 bmd7 bmd3 bmd5 bmd2 bmd6 bmd1 bmd0 bmd4 bmd15 bmd11 bmd13 bmd10 bmd14 bmd9 bmd8 bmd12 bma9 bma8 /bmoe /bmwe bmclk bmd16 bmd20 bmd18 bmd21 bmd17 bmd22 bmd23 bmd19 vdd sduplex1 daisy_in daisy_out lclk nc /rst /test vdd vss vdd ref_clk sduplex0 speed0 speed1 speed2 speed3 speed4 speed5 speed6 speed7 vss vss
asix electronics corporation 7 confidential AX88872P swipeater controller preliminary 2.0 pin description the following terms describe the ax88872 pin out: all pin names with the ? / ? suffix are asserted low. i = input o = output i/o = input /output 2.1 rmii interface for repeater ports 2.1.1 repeater port 0 signal name type pin no. description speed0 i 160 speed select : speed0 is not standard rmii signal. this signal is source from phy to inform repeater whether 10m or 100m speed is auto-nego t iated. active for 10mbps speed is selected depending on power on configuration. crs_dv0 i 161 carrier sense/receive data valid : crs_dv is asserted asynchronously on detection of carrier. crs_dv is asserted by the phy when receive medium is non-idle. loss of carrier shall result in the desertion of crs_dv synchronous to the cycle of ref_clk that presents the first di-bit s of a nibble on to rxd0[1:0]. rxd0[1:0] i 163, 162 receive data : rxd0[1:0] is synchronous to ref_clk rxd0[1:0] shall be ? 00 ? to indicate idle when crs_dv is disserted. value other than ? 00 ? are reserved for out-of-band signaling shall be ignored by mac upon assertion of crs_dv, phy shall ensure that rxd[1:0] = ? 00 ? until proper receive decoding takes place txen0 o 165 transmit enable : txen0 is synchronous to ref_clk. txen0 indicates that mac is presenting di-bits on txd[1:0] for transmission. txen0 shall be negated prior to the 1st ref_clk rising edge following the final di-bit of a frame txd0[1:0] o 168, 167 transmit data : txd0[1:0] shall transition synchronously to ref_clk. txd0[1:0] shall be ? 00 ? to indicate idle when tx_en is disserted. value other than ? 00 ? are reserved for out-of-band signaling shall be ignored by phy. when tx_en is asserted, txd[1:0] are accepted for transmission by phy 2.1.2 repeater port 1 signal name type pin no. description speed1 i 169 speed select : please references section 2.1. 1 port0 description. crs_dv1 i 181 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd1[1:0] i 183, 182 receive data : please references section 2.1. 1 port0 description. txen1 o 184 transmit enable : please references section 2.1. 1 port0 description. txd1[1:0] o 187, 186 transmit data : please references section 2.1. 1 port0 description.
asix electronics corporation 8 confidential AX88872P swipeater controller preliminary 2.1.3 repeater port 2 signal name type pin no. description speed2 i 196 speed select : please references section 2.1. 1 port0 description. crs_dv2 i 202 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd2[1:0] i 204, 203 receive data : please references section 2.1. 1 port0 description. txen2 o 205 transmit enable : please references section 2.1. 1 port0 description. txd2[1:0] o 207,206 transmit data : please references section 2.1. 1 port0 description. 2.1.4 repeater port 3 signal name type pin no. description speed3 i 1 speed select : please references section 2.1. 1 port0 description. crs_dv3 i 2 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd3[1:0] i 4, 3 receive data : please references section 2.1. 1 port0 description. txen3 o 5 transmit enable : please references section 2.1. 1 port0 description. txd3[1:0] o 7, 6 transmit data : please references section 2.1. 1 port0 description. 2.1.5 repeater port 4 signal name type pin no. description speed4 i 9 speed select : please references section 2.1. 1 port0 description. crs_dv4 i 10 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd4[1:0] i 12, 11 receive data : please references section 2.1. 1 port0 description. txen4 o 13 transmit enable : please references section 2.1. 1 port0 description. txd4[1:0] o 15, 14 transmit data : please references section 2.1. 1 port0 description. 2.1.6 repeater port 5 signal name type pin no. description speed5 i 33 speed select : please references section 2.1. 1 port0 description. crs_dv5 i 34 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd5[1:0] i 37,36 receive data : please references section 2.1. 1 port0 description. txen5 o 38 transmit enable : please references section 2.1. 1 port0 description. txd5[1:0] o 40,39 transmit data : please references section 2.1. 1 port0 description.
asix electronics corporation 9 confidential AX88872P swipeater controller preliminary 2.1.7 repeater port 6 signal name type pin no. description speed6 i 41 speed select : please references section 2.1. 1 port0 description. crs_dv6 i 42 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd6[1:0] i 44,43 receive data : please references section 2.1. 1 port0 description. txen6 o 45 transmit enable : please references section 2.1 .1 port0 description. txd6[1:0] o 47,46 transmit data : please references section 2.1. 1 port0 description. 2.1.8 repeater port 7 signal name type pin no. description speed7 i 49 speed select : please references section 2.1. 1 port0 description. crs_dv7 i 50 carrier sense/receive data valid : please references section 2.1. 1 port0 description. rxd7[1:0] i 52,51 receive data : please references section 2.1. 1 port0 description. txen7 o 53 transmit enable : please references section 2.1. 1 port0 description. txd7[1:0] o 55,54 transmit data : please references section 2.1. 1 port0 description. 2.2 mii/rmii interface for switch ports 2.2.1 switch port 0 signal name type pin no. description stxen0 o 87 transmit enable : stxen0 is transition synchronously with respect to the rising edge of stxclk0. stxen0 indicates that the port is presenting nibbles on stxd0[3:0] for transmission. when rmii mode, txen is transition synchronously with respect to the rising edge of ref_clk. stxen0 indicates that the port is presenting nibbles on stxd0[1:0] for transmission. stxd0[3:0] o 91,90,89,88 transmit data : stxd0[3:0] is transition synchronously with respect to the rising edge of stxclk0. for each stxclk period in which stxen is asserted, txd[3:0] are accepted for transmission by the phy. when rmii mode, stxd0[1:0] shall transition synchronously to ref_clk. txd0[1:0] shall be ? 00 ? to indicate idle when tx_en is disserted. value other than ? 00 ? are reserved for out-of-band signaling shall be ignored by phy. when tx_en is asserted, txd[1:0] are accepted for transmission by phy stxclk0 i 93 transmit clock : stxclk0 is a continuous clock that provides the timing reference for the transfer of the stxen0 and stxd0[3:0] signals from the mii port the switch to the phy. sduplex0 i 94 duplex select : duplex0 is not standard mii/rmii signal. this signal is source from phy to inform switch whether 10m or 100m speed is auto-negotiated. scol_sp0 i 97 collision : scol_sp0 is input from phy, when collision is detected.
asix electronics corporation 10 confidential AX88872P swipeater controller preliminary when rmii mode, the signal is stand for speed indicator. active for 10mbps speed is selected depending on power on configuration. scrs0 or scrs_dv i 96 carrier sense : asynchronous signal scrs0 is asserted by the phy when receive medium is non-idle. when rmii mode, the signal is stand for crs_dv (carrier sense/receive data valid ). crs_dv is asserted asynchronously on detection of carrier. crs_dv is asserted by the phy when receive medium is non-idle. loss of carrier shall result in the desertion of crs_dv synchronous to the cycle of ref_clk, which presents the first di-bit of a nibble on to rxd0[1:0]. srxdv0 i 98 receive data valid : srxdv0 is driven by the phy synchronously with respect to srxclk0. asserted high when valid data is present on srxd0[3:0]. srxclk0 i 104 receive clock : srxclk0 is a continuous clock that provides the timing reference for the transfer of the srxdv0 and srxd0[3:0] signals from the phy to the mii port of the repeater. srxd0[3:0] i 114,113, 111,110 receive data : srxd0[3:0] is driven by the phy synchronously with respect to rxclk. when rmii mode, srxd0[1:0] shall transition synchronously to ref_clk srxd0[1:0] shall be ? 00 ? to indicate idle when crs_dv is disserted. value other than ? 00 ? are reserved for out-of-band signaling shall be ignored by mac upon assertion of crs_dv, phy shall ensure that rxd[1:0] = ? 00 ? until proper receive decoding takes place 2.2.2 switch port 1 signal name type pin no. description stxen1 o 60 transmit enable : please references section 2.2.1 switch port0 description. stxd1[3:0] o 64,63,62,61 transmit data : please references section 2.2.1 switch port0 description. stxclk1 i 65 transmit clock : please references section 2.2.1 switch port0 description. sduplex1 i 66 duplex select : please references section 2.2.1 switch port0 description. scol_sp1 i 76 collision : please references section 2.2.1 switch port0 description. scrs1 or scrs_dv1 i 75 carrier sense : please references section 2.2.1 switch port0 description. srxdv1 i 77 receive data valid : please references section 2.2.1 switch port0 description. srxclk1 i 78 receive clock : please references section 2.2.1 switch port0 description. srxd1[3:0] i 82,81,80,79 receive data : please references section 2.2.1 switch port0 description.
asix electronics corporation 11 confidential AX88872P swipeater controller preliminary 2.3 expansion bus interface for 100 mbps signal name type pin no. description hird[3:0] i/o/z /pu 156, 155 154, 153 inter repeater data : nibble data input/output. transfer data from the ? active ? ax88872/3 to all other ? inactive ? ax88872/3 chip s. the bus- master of the ird bus is determined by ir_ a ct bus arbitration. /hird_v i/o/z /pu 152 inter repeater data valid : this signal reflect s the rx_dv status of the active port. used to frame good packets. hird_ck i/o/z /pu 151 inter repeater clock valid : all inter repeater signals are synchronized to the rising edge of this clock. hird_odir o 150 inter repeater data in/out direction : this pin indicates the direction of ird data . ? high ? = h ird[3:0], / h ird_v , h ird_ck are output. ? low ? = h ird[3:0], / h ird_v , h ird_ck are input. /lhir_act[2:0] i/o/oc 128, 126 125 local repeater activity in/out : the function is the same as /hir_acto[3:0] but for local repeater activity only. /hir_acti[3:0] i/pu 132, 131 130, 129 inter repeater activity in: these pins perform the same function as /hir_acto[3:0] when they serve as input function. then the /hir_acto[3:0] insert external buffers the input function must be replaced with /hir_acti [3:0]. /hir_acto[3:0] i/o/oc 148, 147 146, 145 inter repeater activity in/out: the local repeater activity appearance, the signal of the related rid (repeater id) will be asserted and as an output pin. all other pins serve as input pins but except the collision conditions. when collision occur s , the signal of related (rid-1) pins will also serve as outputs and will active during local collision period. the exception case is when rid = 0, then (rid-1) is replaced with (rid+1). 2.4 expansion bus interface for 10 mbps signal name type pin no. description tird[3:0] i/o/z /pu 106, 105 103, 102 inter repeater data : nibble data input/output. transfer data from the ? active ? ax88872/3 to all other ? inactive ? ax88872/3 chip s. the bus- master of the ird bus is determined by ir_ a ct bus arbitration. /tird_v i/o/z /pu 100 inter repeater data valid : this signal reflect s the rx_dv status of the active port. used to frame good packets. tird_ck i/o/z /pu 99 inter repeater clock valid : all inter repeater signals are synchronized to the rising edge of this clock. tird_odir o 95 inter repeater data in/out direction : this pin indicates the direction of data for external transceiver. ? high ? = t ird[3:0], / t ird_v , t ird_ck are output. ? low ? = t ird[3:0], /t ird_v , t ird_ck are input. /ltir_act[2:0] i/o/oc 109, 108 107 local repeater activity in/out : the function is the same as / t ir_acto[3:0] but for local repeater activity only. /tir_acti[3:0] i/pu 119, 118 117, 116 inter repeater activity in: these pins perform the same function as /hir_acto[3:0] when they serve as input function. then the /hir_acto[3:0] insert external buffers the input function must be replaced with /hir_acti [3:0]. /tir_acto[3:0] i/o/oc 124, 123 121,120 inter repeater activity in/out: the local repeater activity appearance, the signal of the related rid (repeater id) will be asserted and as an output pin. all other pins serve as input pins but except the collision conditions. when collision occur s , the signal of related (rid-1) pins will also serve as outputs and will active during local collision period. the exception case is when rid = 0, then (rid-1) is replaced with (rid+1).
asix electronics corporation 12 confidential AX88872P swipeater controller preliminary 2.5 led display signal name type pin no. description led[1:0] o 85, 84 those signals indicate each port ? s statuses (such as a ctivity, jabber and p artition ) and global information(such as collision , repeater id, utilization ) in sequence. for detail , see the led timing specification the utilization of 100m segment and 10m segment are using the same scale . the utilization % display define as following : (see also note 1) 1: led off 0: led on the buffer utilization of internal switch uses the following definition: 1: led off 0: led on led[0] : this signal also indicates sram chip 0 fail ( continue active low ) and 10 0 m repeater collision ( blinking ) during the interval of sequence shift data. led[1] : this signal also indicates sram chip 1 fail ( continue active low ) and 10 m repeater collision ( blinking ) during the interval of sequence shift data. led_ck o 86 led clock : the signal is a discontinue clock for led signals serial shift out. the clock period width is 40 0 ns and last 32 cycle with every 52.4 ms repeated. utilization % uti0 uti1 uti2 uti3 uti4 uti5 0 1 1 1 1 1 1 1 0 1 1 1 1 1 5 0 0 1 1 1 1 10 0 0 0 1 1 1 15 0 0 0 0 1 1 30 0 0 0 0 0 1 60 0 0 0 0 0 0 utilization % uti0 uti1 uti2 uti3 uti4 uti5 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 20 0 0 1 1 1 1 40 0 0 0 1 1 1 60 0 0 0 0 1 1 80 0 0 0 0 0 1 95 0 0 0 0 0 0
asix electronics corporation 13 confidential AX88872P swipeater controller preliminary 2.6 buffer memory pins group signal name type pin no. description bma[16:0] o 197-201 16,17 170,166 143,142 23-18 ssram a ddress bus bmd[31:24] bmd[23:16] bmd[15:8] bmd[7:0] i/o 24, 26-32 133-138 140, 141 171-173 175-179 180, 188-194 ssram d ata bus /bmwe o 158 ssram w rite strobe /bmoe o 159 ssram r ead strobe bmclk o 72 s sram clock
asix electronics corporation 14 confidential AX88872P swipeater controller preliminary 2.7 miscellaneous signal name type pin no. description lclk i 70 local clock : 50- 66mhz. used for system operation synchronous. /rst i 59 reset : active low the chip is reset when this signal is asserted low ref_clk i 68 reference clock : the input is a continuous clock at 50mhz for timing reference with rmii interface. daisy_in i/pu 73 repeater identification number daisy-chain in : when mode= ? 1 ? , this pin is a daisy chain serial input for repeater id. the state machines always monitor s the input if a correct data (rid) present at the pin, the (rid+1) will be written to rid register and override the power on setup rid for the chip. daisy_out o/ml 74 repeater identification number daisy-chain out : when mode= ? 1 ? , this pin is periodically shift out the rid of itself to the next chained chip to inform that this id has already been occupied. the rid is shift out periodically every about 200us. mdio i/o 57 station management data in/ out : for setup phy auto-negotiation registers. a burst write commands are issue to setup phy register after reset. the phy address 4h, 5h, 6h, 7h, 8h, 9h,ah and bh will be written as register 4h to value 00a1h ( advertise register set to 10/100 half-duplex mode)and register 0h to value 1000h(enable auto-negotiation). see also appendix for more information. mdc o 56 station management data clock out : for mdio reference clock. /test i/pu 58 test pin : active low the pin is just for test mode setting purpose only. must be pull high when normal operation. nc o 157 nc : keep no connection vdd i 25, 48 69, 92 122, 144 107, 120 power : +3.3v +/-5% vss i 8, 35 67, 71 83, 101 112,115 127, 139 149, 174 185, 208 power: 0v
asix electronics corporation 15 confidential AX88872P swipeater controller preliminary 2.8 power on configuration setup signals cross reference table signal name share with description /hash_en bma[16] hash algorithm enable : 0 : enable look-up table addressing use hashing algorithm. 1 : disable look-up table addressing use linear addressing aging_s[2:0] bma[15:13] aging timer selection : aging_s2 aging_s1 aging_s0 aging time (min) 1 1 1 no aging (disable) 1 1 0 5 1 0 1 10 1 0 0 20 0 1 1 40 0 1 0 160 0 0 1 640 0 0 0 1 rxfc_en bma[12] pause identification enable : 0 : disable 802.3x receives flow control function in full duplex. 1 : enable 802.3x receives flow control function in full duplex. mii_s1 b ma[11] mii/rmii interface selection for switch p ort 1 : 0 : switch port 1 ? rmii ? mode is selected 1 : switch port 1 ? mii ? mode is selected mii_s0 b ma[10] mii/rmii interface selection for switch p ort 0: 0 : switch port 0 ? rmii ? mode is selected 1 : switch port 0 ? mii ? mode is selected /part_en bma[9] tx partition enable : 0 : enable partition function of transmission. 1 : disable partition function of transmission. ram_s bma[5] ram size selection : external packet buffer ram size select ram_s ram size 1 64k * 32 ssram 0 128k * 32 ssram netqlty_s bma[4] network quality selection: auto forwarding mode is based on packet error percentage to select store -and-f orward or fragment free mode. netqlty_s error packet ratio 1 20% 0 40% fwtyp_s1 fwtyp_s0 bma[3] bma[2] forward type selection : fwtyp _s1 fwtyp _s0 forward mode 1 1 store & forward 1 0 store & forward 0 1 fragment free 0 0 auto hibndy_s1 hibndy_s0 bma[1] bma[0] threshold selection for flow control : flow control will be active when buffer memory is below the threshold: hibndy_s1 hibndy_s0 buffers left 1 1 64 packets 1 0 32 packets 0 1 16 packets 0 0 96 packets / flowctl _en3 stxd0[3] p3 flow control enable : enable flow control function of switch port 3 (link to 10mbps repeater port), back pressure for half duplex. 0 : enable flow control function.
asix electronics corporation 16 confidential AX88872P swipeater controller preliminary 1 : disable flow control function. / flowctl _en2 stxd0[2] p2 flow control enable : enable flow control function of switch port 2 (link to 100mbps repeater port), back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. / flowctl _en1 stxd0[1] p1 flow control enable : enable flow control functions of switch port 1, 802.3x for full duplex, back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. /flowctl_en0 stxd0[0] p0 flow control enable : enable flow control function of switch port 0, 802.3x for full duplex, back pressure for half duplex. 0 : enable flow control function. 1 : disable flow control function. speed_s 2 txd7[ 1 ] speed setting for repeater port 0 to port 7 : 0 : s peed0~7 pin is low for 10m,high for 100m 1 : s peed0~7 pin is low for 100m,high for 10m speed_s1 stxd1[2] speed setting for switch port 1 : it is useful for switch port 1 in rmii mode don ? t care the setting when switch port 1 is in mii mode . 0 : scol_sp1 pin is low for 10m,high for 100m 1 : scol_sp1 pin is low for 100m,high for 10m speed_s0 stxd1[1] speed setting for switch port 0 : it is useful for switch port 0 in rmii mode don ? t care the setting when switch port 0 is in mii mode . 0 : scol_sp0 pin is low for 10m,high for 100m 1 : scol_sp0 pin is low for 100m,high for 10m fdpxhi_s1 stxd1[0] duplex setting for switch port 1 : switch p ort 1 ? sduplex1 ? pin function select 0 : sduplex1 pin is low for half duplex,high for full duplex 1 : sduplex1 pin is low for full duplex,high for half duplex fdpxhi_s0 stxen1 duplex setting for switch port 0 : switch p ort 0 ? sduplex0 ? pin function selection 0 : sduplex0 pin is low for half duplex,high for full duplex 1 : sduplex0 pin is low for full duplex,high for half duplex lrid_s1 lrid_s0 txd5[1] txd5[0] local repeater id select ion : lrid_s1 lrid_s0 lrid no. 1 1 0 1 0 1 0 1 2 0 0 reserved /871_en txen6 ax88871a compatible enable : 0 : enable ax88871a compatible mode 1 : disable ax88871a compatible mode /rdphy_en txd6[0] mdio read phy register 05h information 0 : enable 1 : disable wrphyno_s txd4[1] mdio write phy number selection 1 : mdio write 8 phy address 0 : mdio write 6 phy address ( for 6r+2s application ) wrphyregno_s txd4[0] mdio write phy register number selection 0 : mdio write 2 registers ( 04h, 00h ) 1 : mdio write 3 registers ( 10h, 04h, 00h ) wrphystraddr txd3[1] mdio write phy starting address 0 : mdio write phy from address 18h ( 18h to 1fh ) 1 : mdio write phy from address 04h ( 04h to 0bh ) pktlenopt txd3[0] maximun packet length selection 0 : 1522 byte
asix electronics corporation 17 confidential AX88872P swipeater controller preliminary 1 : 1518 byte all of the above signals are pull-up for default values. note 1 : the calculation formulae of traffic utilization between asix and netcom is difference, so you will get different results when using smartbit (sb) testing this item. we found the smartbit calculate the utilization without include 96 bit time inter frame gap (ifg). so the utilization value can be 100%. as well as we found sb used min packet size (64 byte) and min ifg (96 bit-time) as 100% utilization. in theory, when max packet size (1518 byte) and min ifg the utilization will be more than 100%, but sb also treat it as 100%. in our ax88872 design, we use real cable bandwidth as calculation base. we calculate the bit counts of carrier within a unit time. because of the existence of inter frame gap, in our calculation 100% utilization is impossible. so the above two cases (64 byte packet size and 1518 byte packet size with min. ifg), we will count as 85.7% and 99.2%. if using sb test result to indicate utilization led the value must be modified. see the following reference table. asix ? s utilization% 1 5 10 15 30 60 smartbit ? s utilization% 2 7 12 17 34 68
asix electronics corporation 18 confidential AX88872P swipeater controller preliminary 3.0 functional description 3.1 repeater state machine the repeater state machine is in i dle state when there is no carrier presented on any ports . when there is only one port has receive activity, the repeater state machine will enter d ata - f orwarding st ate to ensure correct data forwarding to other connected ports. if collision happens anytime, the repeater state machine detects collision then send jam pattern to all ports until collision ceases. 3.2 rxe /txe c ontrol idle state crs_dv(all) = 0, the repeater sends no data to any port. rxe(all) = 0. txe(all) = 0. data forwarding state if crs_dv (all) = 1, n is the only one port that has incoming packet. rxe(n) = 1, rxe(allxn) = 0. txe(n) = 0, txe(allxn) = 1. collision state if crs_dv (all) > 1, t he repeater sends jam pattern to all ports. rxe(all) = 0. txe(all) = 1. one port left state when all packets are back off except only one port still has activity, that is crs_dv (all) = 1 again . n is the only one left port that has incoming packet. the repeater sends jam pattern to all other port except for the still activity ports. rxe(all) = 0. txe(allxn) = 1. 3.3 jabber state machine to prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. if a reception exceeds this duration (64k bit times for ax8887 2 ), the jabber condition will be detected. in this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal operation. when the carrier is no longer detected for the jabbered port or reset the repeater, the jabber state will be existed and the port will rece ive and transmi t packets normally . 3.4 partition state machine the partition state machine is used to protect network from being upset when a port suffer continuous
asix electronics corporation 19 confidential AX88872P swipeater controller preliminary collision, each port uses a partition state machine to detect and prevent this condition. when a port suffers from continuous 64 times of collision events, then it goes to partition state. the partitioned port will be not released until a packet without collision be transmitted( more than 512 bit times for ax8887 2 ) or reset the repeater. 3.5 operation of the built-in switch in general, the basic operation of the switch is very simple. the switch receives incoming packets from one of its ports , searches in the look-up table for the destination mac address and then forwards the packet to the destination ports, if appropriate. if the destination mac address is not found in the look-up table, the switch treats the incoming packet as a broadcast packet and forwards it to all ports except itself. basically the switch automatically learns the port number of attached network devices by examining the source mac address of all incoming packets. the device is updated the table with the source mac address if the source mac address does not exist the table. 3.5.1 packet filtering and forwarding process during the receiving process, the switch will monitor the length of the received packet. legal ethernet packets should have a length of no less 64 bytes and nor more than 1528 bytes. the switch discards any packet with illegal length . after a packet is received, its source mac address and destination mac address are received. the source mac address is used to update the look-up table and the destination mac address is used to determine the destination port of the packet. once a mac address has been learned, and the packet is buffered, it must be forwarded, that is, the packet forwarding mechanism for the switch is handled automatically based on the destination mac address. under the following conditions, received packets are filtered: the switch will check all received packets for errors, e.g., fcs error, runt packet, long packet, etc. any packet handing to its own source port will be filtered. that is, its destination port is its source port. the incoming packet will be discarded if the switch ? s buffer memory is full. the switch supports t hree forwarding modes: store- a n d -forward, fragment-free and auto . store- a n d -forward mode: an entry packet is received, checked and stored in the buffer memory before it is forwarded. that is, each forwarded packet is correct. fragment-free mode: it is a simple improvement on cut-through method. the switch will forward a packet whose packet length is more than 64 bytes. all runt packet s will be filtered in fragment-free mode. auto mode: in auto mode, the switch select dynamically its optimized forwarding mode based on the current network quality of each port. 3.5.2 mac address learning and aging process t he switch can learn up to 8k unique mac addresses with a hashing algorithm . addresses are stored in the look-up table located in external ssram, then each packet updates the table . the table lookup engine provides the switching information required routing the data packets. the address table is set up through auto address learning dynamically. after the switch receives a packet , the source mac address and destination mac address are received. the source address retrieved from the received packet is automatically stored in a sa buffer. the switch will check for error and perform a sa search. the switch will update the look-up table with the source mac address if there is no error. the look-up table is cleared on power-on, or hardware reset. when the aging option is enabled, the dynamically learned sa will be cleared if it is not refreshed in less than configured time (2 or 5 min). 3.5.3 flow control process the switch can operate at two different modes: half-duplex and full-duplex. each port can be configured to have flow control enabled or not. the switch supports 802.3x for full-duplex operation and uses back pressure for half-duplex. in full-duplex mode, the switch will receive and transmit the packet in accordance to 802.3x. the transmission channel and the receiving channel operate independently. if the occupancy of the buffer memory is above the flowcontrolactive
asix electronics corporation 20 confidential AX88872P swipeater controller preliminary threshold, the mac of port will send out a pause frame with maximum delay. the switch will send out a pause frame with zero delay after below flowcontrolactive threshold. for the receiving channel, the switch will not transmit the next packet whenever received a pause frame with non-zero delay. the switch will resume packet transmission either after the pause timer expired or a pause frames with zero delay received. in half-duplex mode, the switch will receive and transmit the packet in accordance to 802.3 csma/cd. if the occupancy of the buffer memory is above the flowcontrolactive threshold, the mac of port will send out jam pattern . 3.6 led display interface ax88872 provides per-port led status indication for partition, jabber, activity and support rate - based led for 10 and 100mbps segments utilization (%) and switch buffer utilization (%) . all led[1:0] perform active low. led[1:0] status driver wave-form as follows : jab7 jab6 jab5 jab4 jab3 jab2 jab1 jab0 led_ck led[0] led[0] continue led[1] d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d10 d15 act0 act1 act2 act3 act4 act5 act6 act7 10m uti0 10m uti1 10m uti2 10m uti3 10m uti4 10m uti5 100m uti0 100m uti2 100m uti3 100m uti4 100m uti5 100m uti1 led[1] continue part 7 part 6 part 0 part 1 part 2 part 3 part 4 part 5 sw uti0 sw uti1 sw uti2 sw uti3 sw uti4 sw uti5 sw act0 sw act1 rid0 rid1 rid2 rid3 d16 d19 d20 d21 d22 d18 d23 d17 ( this portation no clock presented ) chip 0 memory test fail and/or 100m collision chip 1 memory test fail and/or 10m collision
asix electronics corporation 21 confidential AX88872P swipeater controller preliminary notes: a. part7~0indicates partition status for each port b. jab7~0 indicates jabber status for each port c. act7~0 indicates activity status for each port d. rid 3 ~0 is the id of repeater chip e. 10m uti5~0 indicate global utilization rate of 10mbps for each 104.8ms sampling period. f. 100m uti5~0 indicate global utilization rate of 100mbps for each 104.8ms sampling period. g. sw uti5~0 indicate global utilization rate of switch packet buffers for each 104.8ms sampling period. h. ram fail : switch ram test fail. it has to use external shift register to decode data on led[ 1 :0]. the application shows as follows: 74ls164(#1) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d rid0 led[0] led_ck 74ls164(#3) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d 74ls164(#2) q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 d act7 act6 act5 act4 act3 act2 act1 act0 100m uti0 10m uti0 100m uti5 100m uti4 100m uti3 100m uti2 100m uti1 10m uti5 10m uti4 10m uti3 10m uti2 10m uti1 rid1 rid2 rid3 fig - 3 application for led display if the user don ? t want to show jabber status, take away the latter 74ls164(#2). the application is the same for led[1].
asix electronics corporation 22 confidential AX88872P swipeater controller preliminary 4.0 internal registers ( this page keep blank)
asix electronics corporation 23 confidential AX88872P swipeater controller preliminary 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts -55 +150 c supply voltage vcc -0.3 +4 v input voltage vin -0.3 vdd+0.5 v output voltage vout -0.3 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +3.0 +3.6 v 5.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss-0.3 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min t yp max units power consumption pc tbd ma note : a. all the input pins without pull low or pull high. b. those pins had been pull low or pull high.
asix electronics corporation 24 confidential AX88872P swipeater controller preliminary 5.4 ac specifications 5.4.1 lclk lclk tr tf tlow bmclk tod symbol description min typ. max units t cyc cycle time 20 ns t high clk high time 8 10 12 ns t low clk low time 8 10 12 ns t r/ t f clk slew rate 1 - 4 ns tod lclk to bmclk out delay 2 ns 5.4.2 reset timing ref_clk /rst symbol description min typ. max units trst reset pulse width 10 - - ref_clk tcyc thigh
asix electronics corporation 25 confidential AX88872P swipeater controller preliminary 5.4.3 rmii interface timing t x & rx t0 t1 ref_clk t2 t3 tx_en txd crs_dv t2 t3 rxd symbol description min typ. max units t0 ref_clk clock cycle time 19.998 20 20.002 ns t1 ref_clk clock high time 7 10 13 ns t2 crs_dv, rxd, txen and txd data setup to ref_clk rising edge 4 ns t3 crs_dv, rxd, txen and txd data hold from ref_clk rising edge 2 ns
asix electronics corporation 26 confidential AX88872P swipeater controller preliminary 5.4. 4 mii interface timing t x & rx t0 t1 txclk t2 t2 tx_en t3 t3 txd symbol description min typ. max units t0 txclk cycle time 39.996 40 40.004 ns t1 txclk high time 14 20 26 ns t2 tx_en delay from txclk high 7.440 21.760 ns t3 txd delay from txclk high 3.410 13.320 ns t4 t5 rx_clk crs t 6 rxdv t 7 rxd rxer symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t 6 crs to rxdv delay requirement 40 160 ns t 7 rxd or rxdv setup to rx_clk rise time 10 - ns
asix electronics corporation 27 confidential AX88872P swipeater controller preliminary 5.4. 5 sram read cycle read cycle bmclk bma[16:0] /bmwr / bmoe bmd[7:0] symbol description min max units t1 clock cycle time 15 - ns t2 address bus setup time 2.5 - ns t3 address bus hold time 0.5 - ns t4 clock to output invalid 2 - ns t5 clock to output valid - 6 ns t5 t4 d1 t3 a1 t2 t1
asix electronics corporation 28 confidential AX88872P swipeater controller preliminary 5.4. 6 sram write cycle bmclk bma[16:0] /bmwr / bmoe bmd[7:0] symbol description min max units t1 clock cycle time 15 - ns t2 address bus setup time 2.5 - ns t3 address bus hold time 0.5 - ns t 4 write data setup time 2.5 - ns t7 write data hold time 0.5 - ns t5 t4 a1 t3 t2 t1 d1 t1
asix electronics corporation 29 confidential AX88872P swipeater controller preliminary 5.4. 7 led display t3 led_ck -------- - ~ ~ ------- d0 d1 d2 .............. d22 d23 d0 d1 d2 t4 t3 led_ck t1 t2 led[1:0] d0 d1 d2 d3 ------- d15 d0 symbol description min typ. max units t1 led setup to led_ck high 190 200 ns t2 led hold from led_ck high 200 210 ns t3 led_ck period width 400 ns t4 led_ck cycle burst out period 52.4 ms 5.4. 8 led display after reset /reset t1 t2 t2 t2 t3 led[2:0] symbol description min typ. max units t1 repeater reset time 1000 ns t2 led blink time after reset 838.4 ms t3 led dark time before normal display 419.2 ms
asix electronics corporation 30 confidential AX88872P swipeater controller preliminary 5.4.9 repeater id daisy chain t1 t2 t2 daisy- out id0 id1 id2 id0 id1 id2 t3 daisy- in id0 id1 id2 id0 id1 id2 symbol description min typ. max units t1 daisy chain one burst period 204.8 us t2 start bit period or data width 12.8 us t3 time-out occur when no data present on daisy_in * 3.8 s note : daisy-chain data-in time-out stands for no input data (always high level) for the specific time.
asix electronics corporation 31 confidential AX88872P swipeater controller preliminary 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.05 0.25 0.5 a2 3.17 3.32 3.47 b 0.10 0.20 0.30 d 27.90 28.00 28.10 e 27.90 28.00 28.10 e 0.50 hd 30.35 30.60 30.85 he 30.35 30.60 30.85 l 0.45 0.60 0.75 l1 1.30 q 0 10
asix electronics corporation 32 confidential AX88872P swipeater controller preliminary appendix a: system applications some typical applications for ax88872 are illustrated bellow. a.1 16-port (24-port) repeater with 2-port switch note : add additional ax88873 to build a 24-port repeater a.2 16-port repeater with up to 4 stacks ax88873 #1 repeater controller buffer 100mbps horizontal cascade 10mbps and 100mbps vertical cascade up to 4 stacks ax88872 #0 swipeater controller 10mbps horizontal cascade 2 quad rmii phy 2 quad rmii phy phy for up-link phy for down-link or server ax88873 #1 repeater controller buffer 100mbps horizontal cascade 10mbps and 100mbps vertical cascade up to 4 stacks ax88872 #0 swipeater controller 10mbps horizontal cascade 2 quad rmii phy 2 quad rmii phy phy for up-link phy for down-link or server ax88873 #1 repeater controller buffer 100mbps horizontal cascade ax88872 #0 swipeater controller 10mbps horizontal cascade 2 quad rmii phy 2 quad rmii phy phy for up-link phy for down-link or server repeater #0 master repeater #3 slave repeater #1,#2 slave (omitted)
asix electronics corporation 33 confidential AX88872P swipeater controller preliminary a.3 8-port standalone repeater with 2-port switch a.4 16-port repeater with up to 4 stacks of ax88871a compatible mode ax88872 #0 swipeater controller 2 quad rmii phy phy for up-link phy for down-link or server buffer 100mbps horizontal cascade 100mbps vertical cascade up to 4 stacks ax88872 #0 swipeater controller 2 quad rmii phy 2 quad rmii phy twin-phy for up- link or down-link ax88872 #1 swipeater controller twin-phy for servers repeater #3 repeater #1,#2 (omitted) buffer 100mbps horizontal cascade ax88872 #0 swipeater controller 2 quad rmii phy 2 quad rmii phy twin-phy for up- link or down-link ax88872 #1 swipeater controller twin-phy for servers repeater #3
asix electronics corporation 34 confidential AX88872P swipeater controller preliminary a.5 16-port repeater with up to 4 stacks and more switch ports note : only the switch ports between 10m and 100m segment of repeater #0/ax88872 #0 are enable buffer 10mbps and 100mbps horizontal cascade 10mbps and 100mbps vertical cascade up to 4 stacks ax88872 #0 swipeater controller 2 quad rmii phy 2 quad rmii phy twin-phy for up- link or down-link ax88872 #1 swipeater controller twin-phy for servers repeater #3 slave repeater #1,#2 slave (omitted) buffer 10mbps and 100mbps horizontal ax88872 #0 swipeater controller 2 quad rmii phy 2 quad rmii phy twin-phy for up- link or down-link ax88872 #1 swipeater controller twin-phy for servers repeater #0 master
asix electronics corporation 35 confidential AX88872P swipeater controller preliminary appendix b: design note b.1 using station management (sta) connection there are two methods to get two switch port speed and duplex information in a x 88872 . one way is by hardware pins such as speed0, sduplex0, speed1, sduplex1 . a x 88872 also provides 2 pins (mdc and mdio , sta ? station management connection ) to read phy auto negotiation remote capability register to get current speed and duplex status. for the phy connected to repeater ports must be configured by sta write function. in a word, a x 88872 use sta read function to get phy register status for switch port and use sta write function to program phy register for hub port. the address setting of phy must be fixed as follows: application 1: 8 hub ports + 2 switch ports application rp : repeater port sp : switch port rp0 rp1 rp2 rp3 rp4 rp5 rp6 rp7 sp0 sp1 04h 05h 06h 07h 08h 09h 0ah 0bh 0fh 10h the corresponding option setting /rdphy_en = 0, wrphyno_s = 1, wrphystraddr = 1 application 2: 6 hub ports + 2 switch ports application rp : repeater port sp : switch port rp0 rp1 rp2 rp3 rp4 rp5 sp0 sp1 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh the corresponding option setting /rdphy_en = 0, wrphyno_s = 0, wrphystraddr = 0
asix electronics corporation 36 confidential AX88872P swipeater controller preliminary b.2 using mii i/f connects to mac there are two ports of ax8887 2 can connect to mac type mii interface. for example, switch port 0 is illustrated bellow. 3.3v 10k * 2 10k gnd ax88 872 / swipeater ax88195 / mac note : 1. the mac needs to run at fullduplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embbeded mac can also refer to this example sduplex0 scol0 stxen0 stxclk0 stxd0[3:0] scrs0 srxdv0 srxclk0 srxd0[3:0] col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock bma[10] stxen1

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